Verilog UART


UART serial port with an AXI4-Stream interface. Includes full MyHDL testbench with intelligent bus cosimulation endpoints. Also includes example makefile-based project targeting a Xilinx Spartan 6 LX 45 on a Digilent Atlys board.



en/verilog/uart/start.txt · Last modified: 2014/11/09 08:27 by alex
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