Verilog AXI Components

Introduction

Collection of AXI bus components. Most components are fully parametrizable in interface widths. Includes full MyHDL testbench with intelligent bus cosimulation endpoints.

  • AXI bus width adapter
  • AXI dual-port RAM
  • AXI synchronous FIFO
  • AXI central DMA
  • AXI nonblocking crossbar interconnect
  • AXI DMA
  • AXI shared interconnect
  • AXI RAM
  • AXI register
  • AXI lite bus width adapter
  • AXI lite dual-port RAM
  • AXI lite synchronous FIFO
  • AXI lite shared interconnect
  • AXI lite RAM
  • AXI lite register

Documentation

Repository

en/verilog/axi/start.txt · Last modified: 2019/02/26 04:02 by alex
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