Verilog AXI Stream Components

Introduction

Collection of AXI Stream bus components. Most components are fully parametrizable in interface widths. Includes full MyHDL testbench with intelligent bus cosimulation endpoints.

  • AXI stream bus width adapter
  • AXI stream synchronous FIFO
  • AXI stream asynchronous FIFO
  • AXI stream synchronous frame FIFO
  • AXI stream asynchronous frame FIFO
  • AXI stream/LocalLink bridge
  • AXI stream rate limiter
  • AXI stream statistics collection

Documentation

Repository

en/verilog/axis/start.txt · Last modified: 2015/01/25 08:57 by alex
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