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en:verilog:axis:start [2014/11/09 08:05] alex [Introduction] |
en:verilog:axis:start [2015/01/25 08:57] (current) alex [Introduction] |
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| Collection of AXI Stream bus components. Most components are fully parametrizable in interface widths. Includes full MyHDL testbench with intelligent bus cosimulation endpoints. | Collection of AXI Stream bus components. Most components are fully parametrizable in interface widths. Includes full MyHDL testbench with intelligent bus cosimulation endpoints. | ||
| - | * AXI stream bus with adapter | + | * AXI stream bus width adapter |
| * AXI stream synchronous FIFO | * AXI stream synchronous FIFO | ||
| * AXI stream asynchronous FIFO | * AXI stream asynchronous FIFO | ||
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| * AXI stream rate limiter | * AXI stream rate limiter | ||
| * AXI stream statistics collection | * AXI stream statistics collection | ||
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| + | ===== Documentation ===== | ||
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| + | [[readme]] | ||
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| ===== Repository ===== | ===== Repository ===== | ||