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en:verilog:start [2019/04/04 06:47]
alex
en:verilog:start [2019/05/28 10:20] (current)
alex
Line 4: Line 4:
   * [[.:axis:]]   * [[.:axis:]]
   * [[.:​ethernet:​]]   * [[.:​ethernet:​]]
 +  * [[.:i2c:]]
   * [[.:​mersenne:​]]   * [[.:​mersenne:​]]
   * [[.:uart:]]   * [[.:uart:]]
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