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en:verilog:pcie:start [2019/07/12 21:29] (current)
alex created
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 +====== Verilog PCIe Components ======
 +
 +===== Introduction =====
 +
 +Collection of PCI express related components. ​ Includes full MyHDL testbench with intelligent bus cosimulation endpoints.
 +
 +===== Documentation =====
 +
 +[[readme]]
 +
 +===== Repository =====
 +
 +  * [[https://​github.com/​alexforencich/​verilog-pcie|Verilog PCIe on GitHub]]
 +
 +===== Links =====
 +
 +  * [[http://​iverilog.icarus.com/​|Icarus Verilog simulator]]
 +  * [[http://​www.myhdl.org/​|MyHDL]]
 +
  
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