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+ | ====== Verilog UART ====== | ||
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+ | ===== Introduction ===== | ||
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+ | I2C interface components. Includes full MyHDL testbench with intelligent bus cosimulation endpoints. | ||
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+ | ===== Documentation ===== | ||
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+ | [[readme]] | ||
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+ | ===== Repository ===== | ||
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+ | * [[http://github.com/alexforencich/verilog-i2c/|Verilog I2C on GitHub]] | ||
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+ | ===== Links ===== | ||
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+ | * [[http://iverilog.icarus.com/|Icarus Verilog simulator]] | ||
+ | * [[http://www.myhdl.org/|MyHDL]] | ||